Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation

The ever expanding market of ultra portable electronic products is compelling the designer to invest major efforts in the development of small and low energy electronic devices. The driving force and benefactors of such devices are (but not limited to) e-health system, sensor network applications, security systems, environmental applications, and home automation systems. These markets have launched a massive trend towards ultra low-energy and ultra low-voltage devices. As the technology scales, the dimensions of a transistors have become extremely small, leading to reliability and process variation issues. Above all, with the ability of placing millions of gates in a small area, high current consumption have become one of the key factors in modern high-performance technologies. In portable electronics, the battery life time is a major issue, as most of the time the device is accompanied with an enclosed battery that has to last for long periods without compromise on performance. Furthermore, there are many applications where the battery lifetime sets the lifetime of the device. Therefore, research is needed to identify the techniques and the impact of them on the design operated for ultra low-energy. The low energy dissipation requirements on a design are achievable by employing various optimization techniques. Voltage scaling is the most effective knob to reduce energy dissipation. For this reason ultra-low energy design usually translates into ultra-low voltage or subthreshold (sub-VT) domain operation. This work presents an analysis on design space for ultra-low energy dissipation of digital circuits. The circuits are operated in the sub-VT region with moderate throughput constraints. The drawback of operating circuits in sub-VT is slow speed performances and reduced reliability. To combat speed degradation due to scaling of the supply voltage, the architectural design space, needs exploration. Techniques such as device sizing, body biasing, stacking transistors, dual threshold gates, multi threshold synthesis, pipelining, and loop unfolding, are explored and applied to the designs. The designs are synthesized in a 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as multi-VT designs. A sub-VT energy model is applied to characterize the designs in the sub- VT domain. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The minimum reliable operation voltage (ROV) for gates in low power 65 nm CMOS technology is found to be around 250 mV. The applied energy model for designs to be characterized for sub-VT domain operation is presented. The energy model encompasses single VT implementations and multi- VT implementations. The energy modeling is based on the 65 nm CMOS standard cells provided by the technology vendor. The energy model has been used to evaluate various techniques and constraints for a circuits operated in the sub-VT domain. The work describes how the energy dissipation of architectures vary w.r.t. switching activity, e. The effects of pipelining together with supply voltage scaling is analyzed, which shows that they have high benefits with respect to energy dissipation. Various half-band digital (HBD) filter structures are evaluated for minimum energy dissipation in the sub-VT domain for a throughput constrained system. All architectures, i.e., unfolded and the basic HBD filter, are implemented and simulated using 65 nm Low-Power High-Threshold (HVT) standard cells. The application of a sub-VT energy model reveals that it is beneficial to use an unfolded implementation to achieve low energy dissipation per sample at EMV, when compared to the energy dissipated by a basic simplified HBD filter implementation. Various available threshold options are analyzed with the help of filter structures by using 65 nm Low-Leakage High-Threshold (HVT), Standard-Threshold (SVT) and Low-Threshold (LVT) standard cells. Secondly, the design space is increased by utilization of a combination of HVT + SVT and also HVT + LVT cells. The analysis with sub-VT energy model leads to the conclusion that a suitable design is a synergy between parallelism, and utilization of various threshold options. In this analysis the multi-VT, implementations did not show a major advantage over single VT implementations. A decimation filter chain consisting of 4 HBD filters is fabricated and the silicon measurements demonstrate that SVT and different architectural flavors are suitable for a ultra low energy (ULE) implementation. Silicon measurements prove functionality down to a supply at 350 mV, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle. Additionally, an alternative to SRAM macro is presented for sub-VT operations. The memory is based on standard-cells and is referred to as SCMs. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT energy characterization model

Reduction of Simultaneous Switching Noise in Analog Signal Band on a Chip

In the era of VLSI the technological advancements have lead us to integrate not only digital circuits of high device density but both digital and analog circuits on to the same chip. In recent years the number of devices on a chip has spectacularly increased, all because of the downward scaling in sizes of the devices. But because of this dramatic scaling the devices have become more sensitive to the power-ground noise. Now in designing a mix signal system within single silicon die that has high speed digital circuits along with high performance analog circuits the digital switching noise becomes a foremost concern for the correct functioning of the system. The purpose of the thesis is to evaluate the reduction of Simultaneous Switching Noise in analog signal band with in the chip. The experiment is done by the use of DCVSL circuits combined with a novel method of implementation, instead of the common static circuits in the core design. These DCVSL circuits have the property to draw periodic currents from the power supply. So if the circuit draws equal amount of current at each clock cycle independent of the input fed to it, the generated noise’s frequency content, produced due to current spikes will then be shifted above the input clock frequency. The idea is to reduce Simultaneous Switching Noise (SSN) by half of the clock frequency in the frequency band. This frequency band often contains to the analog signal band of a digital-to-analog converter. To evaluate the method two pipelined adders have been implemented in 0.13 μm CMOS technology. The proposed method (test circuit) is implemented using DCVSL techniques and the reference circuit using static CMOS logic. For testing of the design we generated the input data on-chip. The pseudo-random data is generated by implementing two different length PRBS. We have also implemented a ROM containing specific test patterns. In the end, we have achieved a 10 dB decrease of noise level at the substrate node on the chip

Power Savings in Digital Filters for Wireless Communication

This paper presents a methodology to reduce the power consumption, silicon area, as well as increasing the performance, in digital filters that are feasible for wireless communication circuitries. The method is based on arithmetic reductions in a wave digital filter. Basically, the multipliers are removed to reduce the number of arithmetic operations. All parameters including the dynamic and static power consumption, the silicon area, as well as the delay time are reduced substantially, without any need for trade-offs. The overall improvements in area, power consumption, and delay time, are around 50%, at an average

Sizing of Dual-V-T Gates for Sub-V-T Circuits

This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively

Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS

This manuscript presents simulation results of energy dissipation in sub-threshold (sub-VT ) of various 16-bit adder structures. The architectures designed for the comparative experiments are, a bit-serial, an 8-bit digit-serial and a 16-bit parallel adder structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. The results show that an energy minimum operating voltage exists for all the three implementations, however the 8-bit digit serial has the least energy minimum operating point. The advantage of the bit-serial structure is that by employing this technique we may save 88% area when compared to parallel implementation and 66% area when compared to digital-serial implementation

A Digital Baseband for Low Power FSK Based Receiver in 65 nm CMOS

The design of a digital baseband for a low power wireless receiver in 65 nm CMOS is presented. It consists of decimation filtering, matched filters for data detection, and preamble based synchronization. The circuit was designed using low threshold devices in both low power (LP-LVT) and general-purpose (GP-LVT) domains. The fabricated circuits were functionally verified, and silicon measurements show a minimum energy dissipation of around 454 pJ and 708 pJ per output bit at a rate of 500 kbit/s for the LP-LVT and GP-LVT implementations, respectively